Field of the Invention
The present invention relates to a method for automatically determining model signals of an FPGA (field-programmable gate array) program, which are readable from the FPGA with the aid of a readback following an FPGA build. The invention also relates to a data processing device, the data processing device being designed to carry out the above method. The invention furthermore relates to a computer program product having computer-implemented instructions, which executes the steps of the above method after being loaded to and run in a suitable data processing device. The invention also relates to a digital storage medium having electronically readable control signals, the control signals being able to interact with a programmable data processing device in such a way that the above method is carried out.
Description of the Background Art
The real-time simulation of complex, dynamic models places strict demands even on modern compute nodes, due the to the tight time constraints. In automotive hardware-in-the-loop (HiL) simulations, models of this type are used primarily where fast control loops need to be closed. This is the case, for example, when simulating in-cylinder pressure sensors, which play an ever greater role in reducing fuel consumption or exhaust gases. However, short cycle times and low latencies are also essential in controlled systems which demonstrate a high level of dynamics, such as electric motors. It is practically no longer possible to implement them using CPU-based simulations.
Field-programmable gate arrays (FPGAs) are able to support computer nodes in the real-time simulation by handling the computation of dynamic parts of a model. Due to the high flexibility and ability to process signals in parallel, the use of FPGAs makes it possible to easily meet even strict real-time requirements. The FPGAs may be used as hardware accelerators for CPUs in compute nodes. One enhancement of this type for an HiL simulator is, for example, the DS5203-FPGA Board from dSPACE. For example, highly dynamic parts of the environment model may be transferred accordingly to the FPGA, so that sufficiently precise and fast response times for the control unit remain ensured. An FPGA hardware configuration, which, borrowing from the creation of general programs, is also referred to as FPGA code, is usually generated in a hardware description language during a build process, based on an FPGA model.
The models of a controlled system are becoming increasingly more complex, due to growing precision requirements, and are thus also difficult to handle. In the automotive HiL environment, models of this type are generally created with the aid of the Matlab/Simulink tool set from The MathWorks Inc. Simulink offers a block-based view of such models in the form of a block diagram. Model parts may be combined into subsystems in a block diagram and linked to each other with the aid of signals. The data flow between these blocks is represented by signal lines.
In a CPU-based real-time simulation, the block diagram of a model is first translated into C/C++ source files with the aid of the Simulink coder. These files are subsequently translated by a compiler into an executable application, which is able to run on a compute node having a real-time-capable operating system. In the CPU build, a trace file is additionally generated, which represents a topology file, including its graphical modeling, for example in Simulink.
As a result of the translation of a model into a CPU application, the computations of the simulation are executed sequentially in a fixed increment. A consistent map of all model states or model variables, such as data on the signal lines or input/output values of the blocks, is thus always present in the main memory of the compute node. Due to the direct access to the main memory, the model variables may be analyzed and/or manipulated in an experiment tool, such as ControlDesk. An optional read/write access to variables of the HiL simulation is possible. Based on the trace files, signal values such as engine speed may be selected and output or manipulated by a display. In the HiL environment, this procedure is summarized under the terms “measure” and “adjust.”
An FPGA-based simulation may be modeled in a block diagram using Simulink, for example with the aid of the Xilinx System Generator (XSG) and the FPGA programming block set from dSPACE, similarly to the CPU-based simulation.
In contrast to the CPU simulation, however, this model is not translated into an iterative programming language but rather into a hardware description language which describes a customer-specific digital circuit. The description of the customer-specific circuit is translated into an FPGA configuration data stream by a synthesis process during the generation of the FPGA code. Accordingly, each model variable which the user wishes to measure or adjust must be guided to the interface of the FPGA over signal lines by means of explicit modeling. Following this adaptation, the model must be retranslated, which can take several hours. This circumstance may result in very long development cycles of FPGA-based real-time simulations.
For some FPGAs, it is possible to freeze and read out the entire status of the FPGA for debugging purposes. Due to the closed input/output behavior of the FPGA, however, it is not possible to randomly access model states, similarly to the main memory of a compute node, i.e., to read out the signals from the FPGA during operation and possibly modify them. A readout of signals from the FPGA may take place, for example, with the aid of a readback, which copies the data from the working level of the FPGA to the configuration level and reads it out from there. Correspondingly, arbitrary register data may, in principle, be read out from the FPGA. Conversely, data may be copied from the configuration level of the FPGA to its working level by means of partial reconfiguration for the purpose of modifying register data. However, not all signals are accessible via registers.
An existing problem in connection with readback is the fact that the signals which may be read back are apparent only at the end of the build process. However, this is problematic, since the process of modeling and building the FPGA program is time-intensive. To make relevant, non-readbackable signals readbackable, and to be able to access all relevant data during operation of the FPGA, an explicit modeling, for example of registers, is required to read out these signals.